1. Field of the Invention
The present invention relates to a method for fabricating a flash memory cell, and more particularly, to a method for fabricating a flash memory cell which simplifies the fabricating process and improves flatness of the device.
2. Discussion of the Related Art
A related method for fabricating a flash memory cell will be explained with reference to the attached drawings. FIGS. 1A-1Y illustrate the process steps of the related method for fabricating a flash memory cell. Each of FIGS. 1A-1Y illustrates cross-sectional views of, from left to right, a control gate of the cell, a crossing part of the control gate and a floating gate, an NMOS transistor formed in a peripheral region, a PMOS transistor formed in a peripheral region, and an HV NMOS transistor, which are hereinafter respectively referred to as first, second, third, fourth and fifth regions in the order.
As shown in FIG. 1A, the related method for fabricating a flash memory cell starts with depositing a buffer oxide film 2 and a nitride film 3 on a semiconductor substrate 1 in succession. Then, a first photoresist film 4 is coated on the nitride film 3 and subjected to selective patterning by exposure and development to remove the first photoresist film 4 in the fourth region totally and a portion of the first photoresist film 4 in the fifth region. The nitride film 3 and the buffer oxide film 2 are removed using the patterned first photoresist film 4 as a mask. N-type ions, such as phosphorus or arsenic, are injected into the semiconductor substrate 1 exposed in the fourth and fifth regions.
As shown in FIG. 1B, after N-wells 5 are formed by a diffusion process, a field oxide film 7 is formed in the fourth region by thermal oxidation. The photoresist film 4, the nitride film 3, and the buffer oxide film 2 are then removed, and boron ions BF.sub.2 are injected into the entire surface. At this time, a thin oxide film 7 is formed on a surface of the semiconductor substrate 1.
As shown in FIG. 1C, a P-well 6 is formed by diffusion. At this time, the N-well 5 is diffused deeper into the semiconductor substrate 1. Then, P-type boron ions are injected into the entire surface to form boron ions in the surface of the semiconductor substrate 1.
As shown in FIG. 1D, a first oxide film 8 is formed on the entire surface. Then, in order to form a buried layer in the first and second regions, a second photoresist film 9 is coated on the first oxide film 8 and selectively patterned. Then, the first oxide film 8 is selectively etched.
As shown in FIG. 1E, after the second photoresist film 9 is removed, an oxide film is deposited on an entire surface and etched back to form first sidewall spacers 10 at both sides of the selectively etched first oxide film 8. Then, arsenic ions are injected into the semiconductor substrate 1 to form a buried region.
As shown in FIG. 1F, after the first oxide film 8 and the first sidewall spacers 10 are removed, a third photoresist film 11 is coated on the entire surface and subjected to patterning to remove the third photoresist film 11 in the first region and the second region. Boron ions are then injected into the exposed surface of the P well 6 to form a channel stop region.
As shown in FIG. 1G, after the third photoresist film 11 is removed, a fourth photoresist film 12 is coated on the semiconductor substrate 1 and subjected to selective patterning to form channel stop regions on both sides of the third region. Boron ions B.sup.+ are injected into the exposed surface of the P well 6 to form the channel stop region.
As shown in FIG. 1H, after the fourth photoresist film 12 is removed, an oxide film is deposited on an entire surface. Then, a fifth photoresist film 13 is coated on the oxide film and patterned. The oxide film is selectively etched to form an isolating oxide film 14 spaced from an upper portion of the buried region formed in the P well 6 in the second region. The isolating oxide films 14 are also formed in regions distinguishing the third, fourth and fifth regions.
As shown in FIG. 1I, after the fifth photoresist film 13 is removed, an oxide film is formed on an entire surface and etched back to form second sidewall spacers 15 at both sides of the isolating oxide films 14.
As shown in FIG. 1J, a first gate oxide film 16 is formed on the entire surface, and a first polysilicon layer 17 is deposited on the first gate oxide film 16. Then, a sixth photoresist film 18 is coated on the polysilicon layer 17 and subjected to selective patterning by exposure and development. Then, the first polysilicon layer 17 is subjected to anisotropic etching using the sixth photoresist film 18 as a mask to expose a portion of each of the buried regions at fixed intervals in the first region to form floating gates 17a and to orient the first polysilicon 17 in one direction in the second region. At this time, defects may occur that may cause a current difference in a reading operation depending on a distance of the floating gate 17a from the buried regions.
As shown in FIG. 1K, after the sixth photoresist film 18 is removed, arsenic ions As.sup.+ are injected into the exposed surface of the substrate to increase on-current of a control gate to be formed later.
As shown in FIG. 1L, a thin tunnel oxide film 19 is formed on the entire surface inclusive of the etched first polysilicon layer 17 and the floating gates 17a.
As shown in FIG. 1M, a second polysilicon layer 20 and a cap oxide film 21 are deposited on the entire surface. Then, a seventh photoresist film 22 is coated on the cap oxide film 21. The seventh photoresist film 22 is subjected to selective patterning by exposure and development to leave the portions of the seventh photoresist film in the first region and between the isolating oxide films 14 in the second region.
As shown in FIG. 1N, the cap oxide film 21 and the second polysilicon layer 20 are subjected to anisotropic etching using the patterned seventh photoresist film 22 to form control gates 20a. Then, the second polysilicon layer 20 and the tunnel oxide film 19 are removed from the third, fourth and fifth regions. A thin oxide film is deposited on the entire surface and etched back to form third sidewall spacers 23 at both sides of the cap oxide films 21 and the control gates 20a and at both sides of the first polysilicon layer 17 in the third, fourth, and fifth regions.
As shown in FIG. 1O, after the seventh photoresist film 22 is removed, an eighth photoresist film 24 is coated and subjected to selective patterning by exposure and development to leave the eighth photoresist film 24 only on the first, and second regions. Then, after removal of the third sidewall spacers 23 at sides of the first polysilicon layer 17 in the third, fourth and fifth regions, the first polysilicon layer 17 is removed to expose the isolating oxide films 14 and the second sidewall spacers 15.
As shown in FIG. 1P, after the eighth photoresist film 24 is removed, a ninth photoresist film 25 is coated and subjected to selective patterning by exposure and development to expose the P well 6 and the N well 5 in the third, and fourth regions. Gate oxide films 26 are formed in the third and fourth regions by oxidation using the patterned ninth photoresist film 25 as a mask. Then, boron ions B.sup.+ are injected thereto.
As shown in FIG. 1Q, after the ninth photoresist film 25 is removed, a tenth photoresist film 27 is coated on the entire surface and subjected to selective patterning to leave the tenth photoresist film 27 only in the third, fourth, and fifth regions. Then, the first polysilicon layer 17 in the second region is subjected to anisotropic etching using the cap oxide films 21 and the control gates 20a as masks to form a floating gate, thereby isolating the floating gates 17a by a cell unit.
As shown in FIG. 1R, after the tenth photoresist 27 is removed, a third polysilicon layer 28 is deposited on the entire surface and an eleventh photoresist film 29 is coated thereon. Then, the eleventh photoresist film 29 is subjected to selective patterning by exposure and development to expose a center porion of the second region and to leave the eleventh photoresist film 29 on portions of the third, fourth and fifth regions in which gate electrodes are to be formed. Then, the third polysilicon layer 28 is subjected to anisotropic etching using the patterned eleventh photoresist film 29 as a mask to form an erasure gate 28a in the second region and gate electrodes 28b in the third, fourth and fifth regions.
As shown in FIG. 1S, the eleventh photoresist film 29 is removed. Then, an oxide film is deposited on an entire surface and etched back to form fourth sidewall oxide films 30 at sides of the erasure gate 28a and the gate electrodes 28b.
As shown in FIG. 1T, a twelfth photoresist film 31 is coated and subjected to selective patterning by exposure and development to leave the twelfth photoresist film 31 in the first, second and fourth regions. Either n-type arsenic or phosphorus ions are injected into the exposed portions of the third and fourth regions to form first source/drain regions 32a and N-type impurity regions 32b.
As shown in FIG. 1U, after the twelfth photoresist film 31 is removed, a thirteenth photoresist film 33 is coated and subjected to selective patterning by exposure and development to expose the fourth region. Then, p-type boron ions BF.sub.2.sup.+ are injected into the fourth region using the patterned thirteenth photoresist film 33 as a mask to form second source/drain regions 34.
As shown in FIG. 1V, the thirteenth photoresist film 33 is removed. Then a second oxide film 35 is deposited, and a flat protection film 36 is deposited on the second oxide film 35.
As shown in FIG. 1W, a fourteenth photoresist film 37 is coated and subjected to selective patterning by exposure and development to expose portions of the first and second source/drain regions 32a and 34, the N- type impurity regions 32b, and the gate electrodes 28b formed on the isolating oxide film 14 in the fourth region. Then, the flat protection film 36 and the second oxide film 35 are subjected to anisotropic etching using the patterned fourteenth photoresist film 37 as a mask to form contact holes.
As shown in FIG. 1X, a tungsten layer is formed on an entire surface and etched back to form tungsten plugs 38 contacting the first and second source/drain regions 32a, 34 and the N-type impurity regions 32b.
As shown in FIG. 1Y, an aluminum layer is deposited on the entire surface and then patterned to form an aluminum wiring layer 39 on the tungsten plugs 38, and the first and second regions.
The above related art flash memory cell has the following problems. First, variation in device electric performance caused by a varying degree of mis-alignment between the buried regions and the floating gates, which occurs during photolithography, degrades operative reliability. Second, as the isolating insulating film is formed by depositing and photolithographying of a CVD oxide film, a flatness of the device becomes poor, thereby decreasing reliability of the following patterning steps. Third, the complicated process with many masking steps leads to a low productivity.